Digital control for a cooking time and power of an electric cooking device

ABSTRACT

A control device adapted to control cooking time and power of an electric cooking device. By depressing entry keys on a control panel a desired cooking time data and power level setting data are entered in first and second shift registers respectively. Next when a cooking start key is depressed the electric cooking device starts its operation at a power corresponding to the power level setting data and the down count operation of the time data in the first shift register is started. When the time data in the first shift register becomes zero due to the down count operation the cooking device stops its operation. The data in the first and second shift registers are displayed by digital indicators. The time data in the first shift register is detected whether or not it has an erroneous digit or digits and any detected erroneous digit or digits are blanked or flashed on the digital indicators.

This is a continuation application of Ser. No. 736,356 filed Oct. 27,1976, now abandoned.

This invention relates to a digital control device for controlling thecooking time and power of an electric cooking device such as anelectronic range, oven etc.

For example, a conventional electronic range uses a mechanical timer andin many cases a magnetron of an electronic range is not powercontrolled. Even when the magnetron is controlled in power level,adjustment is only effected in two steps of "strong" and "weak". In thiscase, however, the power control is effected independently of thesetting of the cooking time and, from the standpoint of manufacture anduse, inconveniences are encountered in the handling and adjustment ofthe cooking device.

It is accordingly the object of this invention to provide a controldevice for an electric cooking device which is free from theabove-mentioned drawbacks and capable of digitally setting, controllingand displaying a power level and cooking time of the cooking device.

According to one aspect of this invention there is provided a digitalcontrol device for controlling the cooking time and power of an electriccooking device comprising first shift register means for storing a timedata on a cooking time of the cooking device; second shift registermeans for storing a data on a power level of the cooking device; meansfor setting the cooking time data and the power level data to the firstand second shift register means, respectively; digital display meanscoupled to the first and second shift register means to display the datastored in the first and second shift register means, subtraction pulsegenerating means for generating a subtraction pulse for eachpredetermined time; subtraction means coupled to the first shiftregister means and the subtraction pulse generating means forsubtracting for each predetermined time a predetermined number from thetime data stored in the first shift register means in response to thesubtraction pulses; cooking device control means coupled to the firstshift register means for operating the cooking device after the storageof data in the first and second shift register means and stopping theoperation of the cooking device when the time data in the first shiftregister means becomes a predetermined number through subtraction; andvariable power control means coupled to the second shift register meansfor setting the cooking device to a power corresponding to the datastored in the second shift register means.

According to another aspect of this invention there is provided adigital control device for controlling cooking time and power of anelectric cooking device comprising a keyboard means having numeral keys,timer key, power level key and cook key; entry means coupled to saidkeyboard means to generate in response to the depression of one of thenumeral keys an output as a numerical data corresponding to thenumerical value of the depressed key; first shift register means havinga plurality of digit stages and adapted to store in response to thedepression of the timer key and numeral keys a time data on a cookingtime of the cooking device which corresponds to the numerical values ofthe depressed numeral keys; second shift register means coupled to theoutput of the entry means to store in response to the depression of thepower level key and numeral keys a data on a power level of the cookingdevice which corresponds to the depressed numeral key; digital displaymeans coupled to the first and second shift register means to displaythe data stored in the first and second shift register means;subtraction pulse generating means for generating a subtraction pulsefor each predetermined time; subtraction means coupled to the firstshift register means and the subtraction pulse generating means andadapted to subtract in response to the depression of the cook key and tothe subtraction pulse and for each predetermined time a predeterminednumber from the time data stored in the first shift register means;cooking device control means coupled to the first shift register meansand adapted to operate the cooking device in response to the depressionof the cook key after the storage in the first and second shift registerof data on the cooking time and power level and stop the operation ofthe cooking device when the data in the first shift register becomes apredetermined number through subtraction; and variable power controlmeans coupled to the second shift register means and adapted to set thecooking device to a power corresponding to the data stored in the secondshift register means.

This invention can be more fully understood from the following detaileddescription when taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a block diagram of an electric cooking device according to oneembodiment of this invention;

FIG. 2 is a time chart of various timing signals used in this invention;

FIG. 3 is a front view of a control panel of the cooking device;

FIG. 4 shows an encoder in FIG. 1;

FIG. 5 shows a control signal generator in FIG. 1;

FIG. 6 shows a gate circuit in FIG. 1;

FIG. 7 shows a timer shift register and subtractor/gate circuit in FIG.1;

FIG. 8 is a diagram useful in explaining the operation of the subtractorof FIG. 7;

FIG. 9 shows an indicating circuit for displaying a time data in a timershift register in FIG. 1;

FIG. 10 is an indicating circuit for displaying a power level settingdata in a power level shift register in FIG. 1;

FIG. 11 shows a clear circuit in FIG. 1;

FIG. 12 is a preset circuit in FIG. 1;

FIG. 13 shows a zero suppression circuit in FIG. 1;

FIG. 14 is an error entry detector in FIG. 1;

FIG. 15 is a flashing circuit in FIG. 1;

FIG. 16 is a data detector in FIG. 1;

FIG. 17 is a magnetron control circuit in FIG. 1;

FIG. 18 is a buzzer operating circuit in FIG. 1;

FIG. 19 is a memory cycle pulse generator in FIG. 1;

FIG. 20 is a waveform diagram for explaining the operation of the memorycycle pulse generator in FIG. 19;

FIG. 21 is a subtraction pulse generating circuit in FIG. 1; and

FIG. 22 shows a variable power control in FIG. 1.

An electronic range including a magnetron will now be explained below byway of example of this invention.

FIG. 1 shows a block diagram of one embodiment of this invention.Reference numeral 1 is a timing pulse generator for generating timingsignals including clock pulses φ₁ and φ₂, bit pulses T₁, T₂, T₄ and T₈and digit pulses D₁ to D₆ and adapted to be applied to each block.Reference numeral 10 is a keyboard including function keys having a cookstart key (hereinafter referred to as a cook key) CK, a cooking timesetting key (hereinafter referred to as a timer key) TM and a powerlevel setting key (hereinafter referred to a power level key) PL and 10entry keys to which decimal numbers 0 to 9 are allotted. An encoder 20is connected to the keyboard section 10 and generates upon depression ofany entry key a binary-coded-decimal data which corresponds to thedecimal number allotted to the entry key. Upon depression of anyfunction key the encoder 20 generates a binary-coded-decimal data otherthan these binary-coded-decimal data allotted to the entry keys, therebydiscriminating which function is depressed.

A control signal generator 30 is connected to the encoder 20 andgenerates a key depression representing signal for indicating thedepression of a function key or an entry key, a signal for indicatingthe depression of the function key, and various control signals when thefunction keys are depressed.

A numerical data generated from the encoder 20 when an entry key isdepressed on the keyboard 10 is entered through a gate circuit 40 into atimer shift register 50 or a power level shift register 60 at the timingof digit pulse D₂. The gate circuit 40 permits the data to be entered inthe timer shift register 50 after the timer key TM is depressed and tobe entered in the power level shift register 60 after the power levelkey PL is depressed. A numerical data obtained when a function key isdepressed is not entered in either of these registers 50 and 60, sincethe gate circuit 40 is disabled by a control signal which is formed bythe control signal generator 30 when the function key is depressed. Thegate circuit 40 is adapted to permit a data to be entered into the timershift register 50 even when the timer key TM is not depressed uponclosure of a power switch.

After a key is depressed on the keyboard a memory cycle pulse generator70 generates in response to a key depression representing signal fromthe control signal generator 30 one memory cycle pulse MCA having awidth which ranges over the digit pulses D₁ to D₆. Since the gatecircuit 40 is enabled during the memory cycle pulse MCA period, even ifa numerical key is continuously depressed, the data is not sequentiallyentered into the register. The memory cycle pulse generator 70 forms amemory cycle pulse MCB even after the key is released. FIG. 2 is a timechart of the memory cycle pulse MC, clock pulse φ₁ and φ₂, bit pulsesT₁, T₂, T₄ and T₈ and digit pulses D₁ to D₆.

In this embodiment, a cooking time is set in terms of minutes (twodigits) and second (two digits) and the power level is set at one of 9levels from 1 to 9. In consequence the power level shift register 60 isconstructed of one digit stage having four bit stages. The timer shiftregister 50 is constructed of seven digit stages, i.e., four digitstages for cooking time setting, two digit stages for a down countoperation and one digit stage for a digit shift at the entry of timedata. Each digit stage of the time shift register is constructed of fourbit stages. Suppose that the four stages for cooking time setting arerepresented by first, second, third and fourth stages, two stages forthe down count operation are represented by fifth and sixth stages, andthe digit pulses D₆, D₅, D₃, D₂ and D₁ corresponds to the first, second,third, fourth, fifth and sixth stages. Since a one-digit time data isentered at a timing of the digit pulse D₂ into the timer shift register50, a tens minute data is entered in the first stage D₆ ; a units minutedata in the second stage D₅ ; a tens second data in the third stage D₄ ;and a units second data in the fourth stage D₃. The fifth digit stage D₂is used for a tenths second data, and the sixth digit stage D₁ for afiftieths second or sixtieth second data. When a cooking time is entered15(1111) is preset in the fifth and sixth digit stages. After completionof the time data entry the first to sixth digit stages forms acirculating shift register.

A subtractor and gate circuit 80 is connected between the timer shiftregister 50 and the gate circuit 40. The timer shift register 50 permitsdata to be circulated through the subtractor and gate circuit 80. Thesubtractor is a half-subtractor and adapted to subtract from a cookingtime data set in the timer shift register 50 a unit time, for example,one second in response to the depression of the cook key CK and tosubtraction pulses from a subtraction pulse generator 90. Thesubtraction pulse generator 90 generates through a 60 or 50 Hz AC supplyone subtraction pulse per cycle of the AC voltage. In this embodimentone pulse per one cycle of AC power supply is generated at timing of D₁·T₂. In the fifth and sixth digit stages of the timer shift register 50are preset such predetermined decimal numbers that each of them becomes15 (all the bits become 1) after down count by the numbers ofsubtraction pulses (D₁ ·T₂) per second. When all of the bits of thefifth and sixth stages become "1", one borrow signal per second isgenerated and one second is subtracted from the cooking time by thisborrow signal.

The down count, i.e., the subtraction of the timer shift register 50 isstopped when the content of the timer shift register 50 becomes "0",when the timer key or the power level key is depressed, or when the doorof the cooking apparatus is opened. Upon depression of the timer key thetimer shift register is cleared. When the power level key is depressedor when the door of the electronic range is opened, the timer shiftregister stops its down count, but the content of the timer shiftregister is maintained. In this case, the down count of the timer shiftregister is restarted by depression of the cook key.

A four-digit digital display 100 for displaying a remaining cooking timedata in the register 50 is connected through a latch circuit 110 to thetimer shift register 50. A one-digit digital display for displaying apower level setting data in the shift register 60 is connected through alatch circuit 130 to the power level shift register 60. FIG. 3 shows acontrol panel of the cooking apparatus including the keyboard 10 anddisplays 100 and 120. Among switches on the control panel, only a powerswitch is of a holding type.

In FIG. 1, reference numeral 140 is a clear circuit 140. The clearcircuit 140 clears the timer shift register 60 when the power switch isclosed and presets a predetermined number, for example, the maximumpower setting data 9 to the power level shift register 60. The clearcircuit is also operated by the timer key to clear the timer shiftregister 50.

Reference numeral 150 is a preset circuit connected to the timer shiftregister 50 and adapted to preset a predetermined number into each digitstage after all the bits of each digit stage of the timer shift registerbecome 1. The number 5 is preset in the first digit stage for a tensminute data; 9, in the second digit stage for a units minute data; 5, inthe third digit stage for a tens second data 9, in the fourth digitstage for a units second data; 9, in the fifth digit stage for a tenthssecond data; and (in case the power supply frequency is 50 Hz) 9, in thesixth digit stage for a fiftieths second data. In a case where the powersupply frequency is 60 Hz, 11 is preset in the sixth digit stage.

Reference numeral 160 is a zero suppression circuit connected to theoutput of the latch circuit 110. The zero suppression circuit 160 isadapted to detect non-significant zero or zeroes in a time data storedin the timer shift register 50 and blank such zero or zeroes on thedisplay 100. When, for example, a data representing "5 minutes and 30seconds" is stored in the timer shift register, the first digit stagestores "0"; the second digit stage, "5", the third stage, "3"; and thefourth stage, "0". Since the "0" in the first stage is a non-significantzero, only the contents in the second, third and fourth digit stages aredisplayed on the display. Before a cooking time is entered in the timershift register the contents of the first to fourth digit stages are all"zero". In this case, the "0" in the fourth digit stage only isdisplayed and zeroes in the first to third digit stages are blanked onthe display.

In this embodiment a maximum time registrable in the timer shiftregister is predetermined and, for example, the maximum time can beselected to be either "59 minutes and 59 seconds" or "15 minutes and 59seconds". If in this case a time exceeding such a maximum time iserroneously set, it is necessary to detect it for notice to the user.Reference numeral 170 is an error entry detection circuit adapted toselect a maximum time settable in the timer shift register and to detectthat a time exceeding such a maximum time had been set in the timershift register. When, for example, the maximum time "59 minutes and 59seconds" is selected, the error entry detection circuit 170 detects thecontents of the first and third digit stages and, if the content of atleast one of the first and third digit stages is 6 or more, it generatesa detection output. When, for example, the maximum time is "15 minutesand 59 seconds", the error entry detection circuit 170 detects thecontents of the first, second and third digit stages and, if the contentof the first stage is two or more and/or if the content of at least oneof the second and third digit stages is 6 or more, it generates adetection output. It is noted, however, that, if the case of the maximumtime "15 minutes and 59 seconds" the content of the first digit stage iszero, the error entry detection circuit does not detect the content ofthe second digit stage in accordance with the output of the zerosuppression circuit 160. The output of the error entry detection circuit170 is applied to the display device 100, thereby blanking the contentof the digit stage or stages which are erroneously entered. This offersthe user an indication as to in which digit stage an erroneous entry ismade. When such an erroneous entry is present, no down count of thetimer shift register is effected and the magnetron is not operated evenupon depression of the cook key. The presence of the error entrydetection circuit prevents an entry of a time which exceeds the presetmaximum time.

Reference numeral 180 is a flashing circuit adapted to, when a timeexceeding the preset maximum time is erroneously entered, flash thedisplay corresponding to a stage or stages associated with the erroneousentry, thereby informing the user of an erroneously entered number ornumbers.

Reference numeral 190 is a buzzer circuit adapted to sound a buzzer 200when a remaining cooking time in the timer shift register 50 becomes,for example, 5 seconds, noticing the user that the cooking time will befinished in five seconds. The sounding of the buzzer is stopped when thecontent of the timer shift register 50 becomes zero.

Reference numeral 210 is a data detector adapted to detect that thecontent of the timer shift register 50 and/or the power level shiftregister 60 is zero.

Reference numeral 220 is a magnetron control circuit including a timerswitch of the magnetron 230. The timer switch is turned ON in responseto the depression of the cook key when a cooking time is correctly setin the timer shift register 50 and the contents of the timer shiftregister 50 and power shift register 60 are both not zero. The downcount of the timer shift register 50 is started by the depression of thecook key and, when as a result of the down count the content of thetimer shift register becomes zero, the timer switch is turned OFF by theaction of the data detector 210.

The output of the power level shift register 60 is applied to a variablepower control circuit 240 to cause the magnetron 230 to be operated at apower corresponding to a numeral value stored in the power level shiftregister. The variable power control circuit 240 includes an astablemultivibrator adapted to subject a magnetron oscillation to an ON-OFFcontrol and selectable resistors in the time constant circuit in themultivibrator for setting an ON-OFF rate (mark-space rate) of an outputof the multivibrator. When one of these resistors is selected by theoutput of the power shift register, the multivibrator oscillates with anON-OFF rate determined by the value of the resistor so selected. Themagnetron repeats its ON-OFF operation by the oscillation of themultivibrator. Since a ratio between the ON time and the OFF time of themagnetron is dependent upon a power level setting data in the powerlevel shift register 60, the output power of the magnetron can becontrolled. A means for controlling the power of the magnetron throughcontrol of the ON-OFF rate of an output of the multivibrator is known inthe art.

Each block in FIG. 1 will now be described in more detail.

FIG. 4 shows the encoder 20. One terminals of each of a power level keyswitch PL, timer key switch TM, cook key switch CK and door switch DR isconnected to an inverter I₁ and through a resistor to a V_(DD) terminal.To the other terminals of these function key switches are appliedcorresponding negative digit pulses as shown. One terminal of each ofkey switches of entry keys 0 to 4 is connected to an inverter I₂ andthrough a resistor to the V_(DD) terminal. One terminal of each of keyswitches of entry keys 5 to 9 is connected to an inverter I₃ and througha resistor to the V_(DD) terminal. To the other terminals of these entrykeys 0 to 9 are applied corresponding negative digit pulses as shown.When no key is depressed, the output of each inverter is at a low level"0". The output of the inverters I₁, I₂ and I₃ is connected respectivelythrough lines KF₁, KN₁ and KN₂ to a logic circuit. The logic circuitincludes OR gates O₁ to O₁₁ to which the corresponding digit pulses areapplied and AND gates A₁ to A₁₁ to which one of the outputs of the ORgates and one of the outputs of the inverters are supplied. The outputsof the AND gates A₁ to A₃ are connected to the set input of a flip-flopcircuit F₁ ; the outputs of the AND gates A₄ to A₆, to the set input ofa flip-flop circuit F₂ ; the outputs of the AND gates A₇ to A₉, to theset input of a flip-flop circuit F₃ ; and the outputs of the AND gatesA₁₀ to A.sub. 11 ; to the set input of a flip-flop circuit F₄. The digitpulse D₂ is applied to the reset terminals of the flip-flop circuits F₁to F₄. The flip-flop circuits F₁ to F₄ are also adapted to receive apulse T₈ φ₁ as a read-in pulse and a pulse φ₂ as a readout pulse.

An AND gate A₁₂ is connected to receive an output Q of the flip-flopcircuit F₁ as well as the digit pulse D₂ and bit pulse T₁ ; an AND gateA₁₃, to receive an output Q of the flip-flop circuit F₂ as well as thedigit pulse D₂ and bit pulse T₂ ; and AND gate A₁₄, to receive an outputQ of the flip-flop circuit F₃ as well as the digit pulse D₂ and bitpulse T₄ ; and an AND gate A₁₅, to receive an output Q of the flip-flopcircuit F₄ as well as the digit pulse D₂ and bit pulse T₈. The outputsof the AND gates A₁₂ to A₁₅ are connected to a NOR gate NO1.

When neither the entry key nor the function key is depressed, theoutputs of the inverters I₁, I₂ and I₃ are all zero and thus the outputsof the AND gates A₁ to A₁₁ are all zero. In consequence, the outputs Qof the flip-flop circuits F₁ to F₄ are all zero and the NOR gate NO1generates an output 15 (1111). At this time the output of the NOR gateNO1 is not entered in the register, since no entry key is depressed,i.e., no memory cycle pulse is generated. Upon depression of the entrykey of numeral 1, the digit pulse D₁ appears at the output of theinverter I₂ and in consequence the digit pulse D₁ appears at the outputsof the AND gates A₄, A₇ and A₁₀. The flip-flop circuits F₂, F₃ and F₄are set by the digit pulse D₁ and the outputs of the flip-flop circuitsF₂, F₃ and F₄ become a logical "1" level after one digit time from thedigit pulse D₁. Since the digit pulse D₂ is being applied to the resetterminals of the flip-flop circuits, the flip-flop circuits are resetafter one digit time from the digit pulse D₂. In this case, the outputsof the flip-flop circuits F₂, F₃ and F₄ are at a logical "1" level onlyduring one digit time of the pulse D₂. Since no digit pulse D₁ isapplied to the set terminal of the flip-flop F₁, the output Q of theflip-flop circuit F₁ is zero. As a result, the outputs of the flip-flopcircuits F₁, F₂, F₃ and F₄ are 0, 1, 1 and 1, respectively. Theseoutputs of the flip-flop circuits are applied to the AND gates A₁₂ andA₁₅, the outputs of which are in turn applied to the NOR gate NO1 wherethey are converted to an output 1 (1000). In the encoder of FIG. 4 thekey input is converted by the flip-flop circuits to a pseudo-code whichis in turn converted by the NOR gate NO1 to a true-code.

Upon depression of the timer key TM the digit pulse D₆ appears at theoutput of the inverter I₁ and thus the digit pulse D₆ appears at theoutput of the AND gate A₆ to set the flip-flop circuit F₂. When thetimer key TM is so depressed, the outputs of the flip-flop circuits F₁,F₂, F₃ and F₄ will be 0, 1, 0 and 0 respectively. This pseudo-code isconverted by the NOR gate NO1 to a true code 1011 (=13), but it is notentered in the register. When the power level key PL is depressed, apseudo code 1000 is formed by the flip-flop circuits F₁ to F₄. Upondepression of the cook key CK a pseudo code 0010 is formed by theflip-flop circuits F₁ to F₄ and when the door of the microwave oven isopened, a pseudo code 1010 is formed by the flip-flop circuits F₁ to F₄.

FIG. 5 shows the control signal generator 30. Each output of theflip-flop circuits F₁ to F₄ is coupled to a NOR gate NO2. When neitherthe function key nor the entry key is depressed, the output of the NORgate NO2 becomes "1". When either of these keys is depressed, the outputof the NOR gate NO2 becomes "0" and in consequence the output of theinverter I₄ becomes "1" to cause an AND gate 16 to generate, at thetiming of D₂, a signal KEY (D₂) indicating that the key has beendepressed. The signal KEY (D₂) is supplied to the memory cycle pulsegenerator 70 to form memory cycle pules MCA and MCB as will be laterdescribed. When the cook key CK is depressed, a NOR gate NO3 generatesan output "1". The output "1" of the NOR gate NO3 is fed through ANDgates A17 and A18 to the set input of a flip-flop circuit F₅ to provideat an output Q a signal (CK) of a logical " 1" level indicating that thecook key has been depressed. When the door of the electronic oven isopened, a NOR gate NO4 generates an output "1". The output "1" of theNOR gate NO4 is delivered through an AND gate A₁₉ and OR gate O₁₂ to thereset input of the flip-flop circuit F₅ to cause the output Q thereof tobe "0". When the timer key TM is depressed, a NOR gate NO5 generates anoutput "1". The output "1" of the NOR gate NO5 is fed through an ANDgate A₂₀ and OR gate O₁₃ to the set input of a flip-flop circuit F₆ toprovide at the output Q thereof a signal (TM) of a logical "1" levelindicating that the timer key TM has been depressed. When the powerlevel key PL is depressed, a NOR gate NO6 generates an output "1" whichis in turn sent through an AND gate 21 to cause the flip-flop F₆ to bereset. The set outputs of the flip-flop circuits F₅ and F₆ aremaintained until these flip-flop circuits are reset. The flip-flopcircuit F₆ is also set by an auto clear signal AC from the clearcircuits 140 as will be later described. The flip-flop circuit F₅ isalso reset when the power level key PL or the timer key TM is depressedor when the power switch is rendered ON.

The flip-flop circuit F₇ is set when the cook key CK is depressed or thedoor of the electronic oven is opened, and reset when the timer key TMor the power level key PL is depressed or when the content of either ofthe timer shift register 50 and power level shift register 60 is zero.The flip-flop circuit F₇, when reset, generates an output L of a logical"1" level. The line KF in FIG. 4 is connected to the set input of aflip-flop circuit F₈. When the function key is depressed the flip-flopcircuit F₈ is set by either one of digit pulses D₂, D₃, D₅ and D₆ andreset by the digit pulse D₁. A flip-flop circuit F₉ is set at the timingof D₁ by the output of the flip-flop circuit F₈ and reset by a pulse D₆T₈. An AND gate A₂₂ is connected to the output Q of the flip-flopcircuit F₉ and generates an output KF·MCA. The output KF·MCA becomes "0"when a function key is depressed, and becomes "1" when a numeral key isdepressed. An AND gate A₂₃ generates a signal L·KF·MCA which becomes "1"when a numeral key is depressed after depression of the timer key or thepower level key. An AND gate 24 generates a signal (TM)·L·KF·MCA whichbecomes "1" when a numeral key is depressed after depression of thetimer key. An AND gate A₂₅ generates L·KF·MCA·D₂.

FIG. 6 shows the gate circuit 40. A data input from the encoder 20 andthe output L·KF·MCA·D₂ of the abovementioned AND gate A₂₅ is coupled toAND gates A₂₆ and A₂₇. The time key depression representing signal (TM)from the flip-flop circuit F₆ is coupled to the AND gate A₂₆ and thesignal (TM) is coupled to the AND gate A₂₇. Since the signal (TM) andL·KF·MCA·D₂ are both at a logical "1" level when a numeral key isdepressed after depression of the timer key, the output of the encoderis entered, through the AND gate A₂₆, into the timer shift register 50.When the power level key PL is depressed, the flip-flop circuit F₆ inFIG. 5 is reset to cause the signal (TM) to become zero. Since thesignal (TM) is at the logic "1" level, the output of the encoder isentered, through the AND circuit A₂₇, into the power level shiftregister 60. Because the signal L·KF·MCA·D.sub. 2 is zero when afunction key is depressed, the function key input from the encoder 20 isnot entered into either of the registers. Since the signal L is anoutput Q of the flip-flop circuit F₇ in FIG. 5 it becomes zero when theflip-flop circuit F₇ is reset by the depression of the cook key CK.Therefore, even if a numeral key is depressed after depression of thecook key, the numeral data of the key being depressed is not enteredinto the register. The same is true when the door of the electronic ovenis opened.

The timer shift register 50 and subtractor and gate circuit 80 will beexplained below by referring to FIG. 7.

The timer shift register 50 includes D₆, D₅, D₄, D₃, D₂ and D₁ digitstages 51, 52, 53, 54, 55 and 56 and a digit stage 57 for one-digitshifting at the numeral data entry time. Since an normal state otherthan at the entry time, the signal (TM)·L·KF·MCA from the AND gate A₂₄in FIG. 5 is zero. An AND gate A₂₈ is disabled and an AND gate 29 isenabled. Accordingly the content of the timer shift register 50 iscirculated through the AND gate A₂₉, OR gate O₁₄, AND gate A₃₀, OR gateO₁₅, AND gate A₃₁, AND gate A₃₂ and OR gate O₁₆. Since at the entry timethe signal (TM)·L·KF·MCA is at the logical "1" level, the AND gate A₂₈is enabled and the AND gate 29 is disabled. As a result, the digit stage57 is coupled between the D₆ stage 51 and the D₅ stage 52 so that shiftby one-digit place can be effected at the entry time. At the entry time,the AND gate A₃₀ is disabled at the timing of D₂ and thus the content ofthe D₂ stage 55 is erased. A time data from the gate circuit 40 isentered at the timing of D₂ into the D₆ digit stage 51 through OR gateO₁₇, OR gate O₁₅, AND gate A₃₁, AND gate A₃₂ and OR gate O₁₆. After onememory cycle, the content of the D₆ digit stage 51 is stored in the D₃digit stage 54. After completion of entry, a tens minute data is presentin the D₆ stage 51; a units minute data, in the D₅ stage 52; a tenssecond data, in the D₄ stage 53; and a units second data, in the D₃stage 54. Because at completion of entry a signal (TM)·L·MCB is at alogical "1" level, an AND gate A₃₃ is enabled and thus the data 15(1111) is stored in the D₂ and D₁ stages 55 and 56 by the digit pulsesD₁ and D₂. When the power source is thrown ON or the timer key TM isdepressed a CLEAR signal is at a logical "0" level, the AND gate A₃₁ isdisabled and thus the time shift register 50 is cleared. By depressionof an entry key the CLEAR signal becomes a logical "1" level to enablethe AND gate A₃₁.

The count down operation of the timer shift register 50 will now beexplained below.

When a time data and power level setting data are entered in the timershift register 50 and power level shift register 60, the output of thedata detector 210 becomes a logical "1" level. When in this state thecook key is depressed, (CK) signal becomes "1". As a result, an AND gateA₃₄ is enabled and one subtraction pulse D₁ T₂ per fiftieth or sixtiethsecond is supplied to the subtractor. The subtraction pulse is generatedat the timing of D₁ T₂. The subtractor compares the subtraction pulsewith the content of the twos bit position in the D₁ stage 56. Where thesubtraction pulse appears at the output of an OR gate O₁₈ the content ofthe twos bit (T₂) position of the D₁ stage 56 appears at the output ofthe AND gate A₃₁. When the outputs of the OR gate O₁₈ and AND gate A₃₁are both at the logical "1" level the outputs of the AND gates A₃₂ andA₃₅ are both at the logical level "0". Accordingly, when the content ofthe D₁ stage 56 is entered in the D₆ stage the content in the twos bitposition of the D₆ stage 51 becomes a logical "0" level. When the outputof the OR circuit O₁₈ is at the logical "1" level and the output of theAND gate A₃₁ at the logical "0" level, the AND gate A₃₅ generates anoutput "1" which is fed through the OR gate O₁₆ to the D₆ stage 51. Thatis, the content in the twos bit position of the D₁₆ stage becomes "1".The output "1" of the AND gate A₃₅ is applied to one-bit shift registerS₁ and the output "1" of the shift register S₁ is fed as a borrow digitto the OR gate O₁₈ through an AND gate A₃₆. Then, the borrow digit iscompared with the content in the fours bit position of the D₁ stage 56.When the output of the OR circuit O₁₈ is zero, the AND gate A₃₂ isenabled and the content in the D₁ stage 50 is delivered to the D₆ stage51.

As will be evident from the foregoing subtractor permits an output "0"to be delivered to the D₆ stage 51 when the outputs of the OR circuitO₁₈ and AND gate A₃₁ are both at a "1" level, permits a borrow to occurand an output "1" to be supplied to the D₆ stage 51 when the output ofthe OR circuit D₁₈ is at a "1" level and the output of the AND gate A₃₁is at a "0" level, and permits an output "1" or "0" to be delivered tothe D₆ stage 51 according to the content of the D₁ stage 56 when theoutput of the OR circuit O₁₈ is at a "0" level. In the D₁ and D₂ stagesare preset such numbers that down count operation of the D₁ and D₂stages by the number of subtraction pulses occurring during one secondpermits to subtract one second from the units second data stored in theD₃ stage 54. At the completion of entry, 15(1111) are set in the D₁ andD₂ stages as mentioned above, but by the preset circuit 150 as will belater described a data in the D₂ stage is converted to 9 (1001) and adata in the D₁ stage is converted to 9 in the case of a 50 Hz powersource frequency and to 11(1101) in the case of 60 Hz power sourcefrequency. As a consequence in the case of the 50 Hz power sourcefrequency a borrow as subtracting one second from a data in the D₃ stageoccurs by fifty substraction pulses per second and in the case of 60 Hzpower source frequency a borrow as subtracting to one second from a datain the D₃ stage occurs by sixty subtraction pulses per second. In the 50Hz power source frequency the down count operation will be evident fromFIG. 8. FIG. 8 shows the case where 1(1000), that is, one second isstored in the D₃ stage.

Upon depression of the cook key CK a flip-flop circuit F₁₀ is reset,causing an output of an inverter I₅ to become "1" to enable the AND gateA₃₆. As a result, a borrow signal is supplied from the shift register S₁to the AND gate A₃₅ to permit a down count operation. As will be evidentfrom FIG. 5, when the timer key TM or the power level key is depressedduring the down count operation or when the door of the oven is openedthe (CK) signal becomes zero, causing the AND gate A₃₆ to be disabled.Since a supply of a borrow to the AND gate A₃₅ is stopped the down countoperation is stopped. When the power level key is depressed or the doorof the oven is opened the content in the timer shift register is heldand upon again depressing the cook key the down count operation isrestarted. Since, however, a CLEAR signal becomes zero upon depressionof the timer key the content in the timer shift register is erased. Whenan erroneous time data is entered in the timer shift register theflip-flop circuit F₁₀ is set by an output N₁ of the error entrydetection circuit 170. As a result, the output of the inverter I₅becomes zero at the timing of D₃ to cause the AND gate A₃₆ to bedisabled and a supply of a borrow to the AND gate A₃₆ is interruptedduring the digit pulse D₃ time. This means that in the erroneous entrythe D₁ and D₂ stages undergo a down count operation, but that thecooking time data in the timer shift register 50 is not counted down.

FIG. 9 shows the display 100 for displaying a data in the timer shiftregister 50. The latch circuit 110 is connected to the D₆ stage 51 inthe timer shift register and adapted to receive a pulse T₈ φ₁ as aread-in pulse and a pulse φ₂ as a readout pulse. A data in the D₆ stage51 appears at the output of the latch circuit 110 with a one-digit timedelay. A known decoder driver 101 having a blanking input is connectedto the outputs of the latch circuit 110. The outputs of the decoderdivider 101 are connected to seven-segment digital indicators 102, 1043,104 and 105 each having light-emitting-diodes. The indicators 102, 103,104 and 105 are adapted to display tens minute data, units minute data,tens second data and units second data, respectively. The indicators102, 103, 104 and 105 are connected respectively through transistors Q₁,Q₂, Q₃ and Q₄ to ground. The digit pulse D₁ is applied to the base oftransistor Q₁, the digit pulse D₆ to the base of transistor Q₂, thedigit pulse D₅ to the base of transistor Q₃ and the digit pulse D₄ tothe base of transistor Q₄.

At the timing of D₁ tens minute data appears at the outputs of the latchcircuit 110. Since at this time the transistor Q₁ is turned ON theindicator 102 displays the tens minute data. Since at the timing of D₆units minute data appears at the outputs of the latch circuit 110 theindicator 103 displays the units minute data. The tens second data andunits second data are displayed at the timing of D₅ and D₄,respectively.

FIG. 10 shows the display 120 for displaying a data in the power shiftregister 60. The latch circuit 130 is connected to the outputs of thepower level shift register 60. A decoder driver 121 is connected to theoutputs of the latch circuit 130 and the output of the decoder 121 isgrounded through a 7-segment indicator 122 constituted of light emittingdiodes.

The display of the timer shift register 50 of FIG. 9 is of a dynamictype and the display of the power level shift register 60 of FIG. 10 isof a static type. However, a dynamic type display can be used for thepower level shift register. In this case, a transistor is connectedbetween the indicator 122 and ground and one of digit pulses D₁ to D₆may be supplied to the base of this transistor.

FIG. 11 shows the clear circuit 140. When the power switch is renderedON, a power supply circuit 141 generates a pulse to cause a flip-flopcircuit F₁₁ to be set. The flip-flop circuit F₁₁ generates an AUTO CLEARsignal of a "1" level, enabling an AND gate A₃₇ to permit 9(1001) to beset in the power level shift register 60 by bit pulses T₁ and T₈. Adesired power level setting data as set by an entry key after depressionof the power level key can be entered into the shift register 60 throughan OR circuit O₁₉. A flip-flop circuit F₁₂ is set by the AC signal fromthe flip-flop circuit F₁₁ to generate a CLEAR signal of a logical "O"level at the Q output thereof, disabling the AND gate A₃₁ in FIG. 7 toclear the timer shift register 50. It will be apparent that because theflip-flop circuit F₁₂ can be set even by a signal TM(D₂) representingthe depression of the timer key the timer shift register 50 is clearedby the depression of the timer key. That is, the timer key is used as aclear key. The flip-flop circuit F₁₁ is reset by a signal MCA asobtained by the depression of a key. From this it will be clear thatduring entry the AND circuit A₃₇ is disabled. The flip-flop circuit F₁₂is reset by the signal KF·MCA from the AND gate A₂₂ in FIG. 5 whichrepresents the depression of an entry key. It will be evident thatduring entry the AND gate A₃₁ (FIG. 7) is enabled to cause a time dataas set at the keyboard to be entered in the timer shift register.

FIG. 12 shows the preset circuit 150. All the bits of each stage in thetimer shift register 50 become zero during the down count operation andthen become one upon receipt of next borrow. The preset circuit 150 isadapted to detect such a state that all the bits of the stage are oneand preset a predetermined number in the stage. That is, 9 is preset inthe D₅ stage for the units minute data; 5, in the D₄ stage for the tenssecond data; 9, in the D₃ stage for the units second data; 9, in the D₂stage for the tenths-second data; and 9 (in the case of the 50 Hz powersource frequency), in the D₁ stage for the fiftieth of sixtieth seconddata and 11 (in the case of the 60 Hz power source frequency), in the D₁stage.

In FIG. 12 an AND gate A₃₉ detects that all the bits of the D₆ stage 51are one. For example, a data in the D₁ stage 56 is entered at the timingof D₁ in the D₆ stage 51. If, therefore, all the bits of the D₁ stage 56are one, the AND gate A₃₉ generates an output "1" during the D₁₀ T₄ toD₁ T₉ time period. The output of the AND gate A₃₉ is read by a T₈ φ₁pulse into a shift register S₂ and read by a φ₂ pulse out of the shiftregister S₂. In consequence the output of the shift register S₂ is heldat a "1" level during the digit pulse D₂ time period, enabling an ANDgate A₄₀. The output of an inverter I₆ becomes zero during the digitpulse D₂ time period, disabling the AND gate A₂₉ (FIG. 7) to cause thecontent 1111 in the D₁ stage 56 to be erased. An AND gate A₄₂ is enabledby the digit pulse D₂ through OR gates O₂₁ and O₂₂ from an AND gate A₄₁to provide an output of 9(1001) at the output of AND gate A₄₀ by the bitpulses T₁ and T₈. The output of AND gate A₄₀ is coupled to the OR gateO₁₄ in FIG. 7. This means that the content in the D₆ stage 51 (all thebits are one) has been converted to 9 when shifted at the timing of D₂to the D₅ stage 52. The AND gate A₄₂ is enabled by the digit pulses D₃,D₄ and D₆, too and, thus when all the bits of each of the D₂, D₃ and D₅stages 55, 54 and 52 are one, these stages are preset to 9,respectively. Since an AND gate A₄₃ is enabled by the digit pulse D₅,the D₄ stage 53 is preset by bit pulses T₁ and T₄ to 5 when all the bitsof the D₄ stage 53 are one. A switch SW₁ is adapted to switch the presetvalue of the D₁ stage to 9 or 11 according to the power sourcefrequency. When the switch SW₁ is in a position shown in FIG. 12 the ANDgate A₄₁ is enabled to cause 9 to be preset to the D₁ stage as mentionedabove. When the switch SW₁ is thrown to the other side, an AND gate A₄₄is enabled and the AND gate A₄₁ is disabled. In consequence a data11(1101) is preset by bit pulses T₁, T₂ and T₈ in the D₁ stage. Theswitch SW₁ is inaccessible by the user.

FIG. 13 shows the zero suppression circuit 160. At the timing of D₆ atens minute data is present in the D₆ stage 51. When the tens minutedata is zero the bit outputs of the latch circuit 110 become zero duringthe digit pulse D₁ time period after the one-digit time. Because at thistime the output of the NOR gate NO7 becomes 1, the output of an ANDcircuit A₄₆ becomes 1 during the digit pulse D₁ period. The output "1"of the AND gate A₄₆ is supplied through OR gates O₂₃ and O₂₄ to theblanking input of the decoder driver 101 to blank the tens minute dataof "0". A flip-flop circuit F₁₃ is set by the output "1" of the AND gateA₄₆ to generate an output "1". A units minute data is fed at the timingof D₅ to the D₆ stage 51. With a one-digit time delay the units minutedata appears at the timing of D₆ at the outputs of the latch circuit110. When the units minute data is zero the output of the NOR gate NO7becomes "1" and thus during the digit pulse D₆ period an AND gate A₄₇generates an output "1". The output "1" of the AND gate A₄₇ is connectedto the blanking input of the decoder driver 101 to cause the unitsminute data "0" to be blanked. If the units minute data is not zero, theoutput of the NOR gate NO7 is zero and in consequence the output of theAND gate A₄₇ is zero. In this case, the units minute data is displayed.When the tens minute data and units minute data are both "0", aflip-flop circuit F₁₄ is set by the output of the AND gate A₄₇. A tenssecond data is entered at the timing of D₄ in the D₆ stage 51 and itappears at the timing of D₅ at the outputs of the latch circuit 110.When the tens second data is "0" the output of the NOR gate NO7 is at alevel "1" and thus an AND gate A₄₈ generates a "1" level output at thetiming of D₅. In consequence, when the respective tens minute, unitsminute and tens second data are zero the "0" of the tens second data isblanked. When the units minute data is not "O" even if the tens seconddata is "0" the output of the AND gate A₄₇ is at a "0" level.Accordingly, since the flip-flop circuit F₁₄ is not set the "0" of thetens second data is displayed. When the respective tens minute, unitsminute, tens second and units second data are zero, the tens minute,units minute and tens second data are blanked, but the units second dataof "0" is displayed.

FIG. 14 shows the error entry detector 170. The maximum time settable inthe timer shift register 50 can be set to either one of the times "15minute and 59 second" and "59-minute and 59-second" by a switch SW₂. Theswitch position shown in FIG. 14 selects the time "15-minute and59-second". The switch SW₂ is also inaccessible by the user.

When the maximum time "15-minute and 59-second" is set the error entrydetector 170 detects whether the tens minute data is two or more orwhether the units minute and tens second data are, respectively, 6 ormore. When the maximum time "59-minute and 59-second" is selected, theerror entry detector 170 detects each of the tens minute and tens seconddata is six or more. Accordingly the error entry detector 170 includes acircuit 171 for detecting a data of 2 or more and a circuit 172 fordetecting a data of 6 or more.

Suppose that the maximum time "15-minute and 59-second" is set. When inthis case two or more tens minute data are fed at the timing of digitpulse D₆ to the D₆ stage 51 the output of an OR gate O₂₅ becomes "1",enabling an AND gate A₅₀. In consequence the output of the AND gate A₅₀becomes "1" during the digit pulse D₆ time period. The "1" level outputof the AND gate A₅₀ is fed to a shift register S₃ adapted to receive aT₈ φ₁ pulse as a read-in pulse and a φ₂ pulse as a readout pulse. Inconsequence the output of the shift register S₃ is at a "1" level duringthe digit pulse D₁ period. The "1" level output of the shift register S₃is applied to an AND gate A₄₉ in FIG. 13 through an AND gate A₅₁ beingenabled by the SW₂ and through an OR gate O₂₆. Since the output of theAND gate A₄₉ is coupled through the OR circuit O₂₄ to the blanking inputof the decoder driver 101, two or more tens minute data is blanked.

When in the case of the maximum time "15-minute and 59-second" the unitsminute data is 6 or more the output of circuit 173 becomes "1", enablingan AND gate A₅₂ to generate an output "1". As a result, an AND gate A₅₃is enabled. Since AND gate A₅₄ is enabled by the switch SW₂ the digitpulse D₅ is applied through an OR O₂₇ to the AND gate A₅₃. Accordingly,the output of the AND gate A₅₃ is at a "1" level during the digit pulseD₅ period. The output "1" of the AND gate A₅₃ is applied to a shiftregister S₄ adapted to receive a T₈ φ pulse as a read-in pulse and a φ₂pulse as a readout pulse. The output of the shift register is at a "1"level during the D₆ digit pulse period.

To the error entry detector 170 are applied from the zero suppressioncircuit 160 the output M of the flip-flop circuit F₁₃ (FIG. 13) whichbecomes "1" when the tens minute data is zero, as well as the output Nof the flip-flop circuit F₁₄ (FIG. 13) which becomes "1" when the tensminute and units minute data are both zero.

When in the case of the maximum time "15-minute and 59-second" the tensminute data is 1 or more an AND gate A₅₅ is enabled due to the presenceof an inverter I₇. The output of the AND gate A₅₅ is at a "1" levelduring the digit pulse D₆ period, since the output of the shift registerS₄ is at a "1" level when the units minute data is 6 or more. The output"1" of the AND gate is fed through the OR gate O₂₆ to the blanking inputof the decoder driver 101 to blank 6 or more units minute data. The samething is applied to the case where the tens minute data is 1, or 2 ormore. However, in a case where the tens minute data is zero, even if theunits minute data is 6 or more, the units minute data is not judged asan erroneously entered number. In a case where the tens minute data iszero, since the M signal is 1, the output of an AND gate A₅₆ is at a "1"level during the digit pulse D₅ period. Since the digit pulse D₅ issupplied through the AND gate A₅₄ and OR gate O₂₇ to the AND gate A₅₃,even when the units-minute data is 6 or more, the output of the AND gate53 produces a "1" level output during the digit pulse D₅ period when theunits minute data is 6 or more. In consequence, the output of the shiftregister S₄ is at a "1" level during the digit pulse D₆ period. For thisreason, digit pulse D₅ and D₆ are applied to the AND gate A₅₅. Since,however, these digit pulses D₅ and D₆ are displaced in time from eachother, the AND gate A₅₅ generates no "1" level output. As a result, whenthe tens minute data is zero, 6 or more units minute data is displayed.Next when the tens second data is 6 or more, the output of the AND gateA₅₃ is at a "1" level during the digit pulse D₄ period and the output ofthe shift register S₄ is at a "1" level during the digit pulse D₅period. Since the AND gate A₅₅ is enabled by the N signal when the tensminute and units minute data are both zero, by an M signal when the tensminute data is not zero, and by the digit pulse D₅ when the tens minutedata is zero. When the tens second data is 6 or more, the AND gate A₅₅produces a "1" level output during the digit pulse D₅ period. That is,even when the tens minute and units minute data take any number,respectively, 6 or more tens second data is judged as an error entry andnot displayed. When the maximum time is set to "59-minute and59-second", the AND gate A₅₁ is disabled and the output of the detectioncircuit 171 adapted to detect a data of 2 or more is not supplied to theOR gate O₂₆. Since in the case of the maximum time "59-minute and59-second", an AND gate A₅₇ is enabled, the AND gate A₅₃ produces a "1"level output during the digit pulse D₆ period when the tens minute datais 6 or more. Accordingly, the shift register S₄ generates an output "1"during the digit pulse D₁ period. Since the AND gate A₅₅ is beingenabled by the M signal, it generates an output "1" during the digitpulse D₁ period and in consequence 6 or more tens minute data is notdisplayed.

In the case of 6 or more tens second data, the AND gate A₅₃ generates anoutput "1" during the digit pulse D₄ period and thus the shift registerS₄ generates an output "1" during the digit pulse D₅ period. The ANDgate A₅₅ generates an output "1" during the digit pulse D₅ period. Thatis, even when the tens and units minute data are any number 6 or moretens second data is judged as an erroneous data and not displayed.

In the circuit arrangement shown in FIG. 14 an NAND gate NA2 is providedso as not to operate the data detection circuits 171 and 172 when thecontent in each digit stage becomes 15(1111). That is, when the data is15, the NAND gate NA2 generates an output "0", disabling the AND gatesA₅₀ and A₅₂.

FIG. 15 shows the flashing circuit 180. As will be evident from FIG. 8,during the down count operation the content in the D₂ stage i.e., tenthssecond data, is sequentially varied from 9 to 0 during one second. Whenthe data in the D₂ stage is 7, 6, 5 and 4, the fours bit (T₄) becomes"1". That is, when the period when the fours bit is "1" continues forfour tenth second per second. The data in the D₂ stage that is, thetenths second data, is entered in the D₆ stage 51 at the timing of D₂.When the data in the D₆ stage is at least 7, 6, 5 and 4, a NAND gate NA3generates an output "1". In consequence, when the tenths second databecomes 7, an AND gate A₅₇ generates an output "1", setting a flip-flopcircuit F₁₅. In consequence, the flip-flop circuit F₁₅ generates anoutput "1" at the timing of D₃. When the tenths data becomes 3, thefours bit becomes zero and thus an AND gate A₅₈ generates an output "1",resetting the flip-flop circuit F₁₅. That is, the output "1" of theflip-flop circuit F₁₅ continues for four tenth second period i.e. duringa time period in which the tenths second data is 7, 6, 5 and 4 andduring the remaining six tenth second period the output of the flip-flopcircuit F₁₅ becomes zero. As shown in FIG. 13 the output of theflip-flop circuit F₁₅ is supplied, together with the cook key depressionsignal (CK), to an NAND gate NA1 the output of which is connected to theAND gate A₄₉. That is, when the cook key CK is being depressed, theoutput of the NAND gate NA1 becomes zero during the four tenth second.The AND gate A₄₉ to which the output of the error entry detector iscoupled is disabled by the output of the NAND gate NA1 and thus theoutput of the error entry detector is not coupled to the blanking inputof the decoder driver 101 during a four tenth second. In consequence, attime intervals of sixth tenth second an erroneous data is displayed forfour tenth second. That is, although when the erroneous data is storedin the timer shift register, it is not displayed by the action of theerror entry detector, the erroneous data can be intermittently displayedby depression of the cook key CK under the action of the flashingcircuit, thereby clearly informing the user of the number of theerroneous data. Since when all the bits in the D₆ stage 51 are "1" theNAND gate NA3 produces an output of a "0" level, the flip-flop circuitF₁₅ is not set. As the NAND gate NA3 in FIG. 15 the NAND gate NA2 inFIG. 14 may be used.

FIG. 16 shows the data detector 210. Since a flip-flop circuit F₁₆ isreset by digit pulse D₁ or D₂ the Q output thereof is necessarilyrendered zero at the timing of D₁ ·T₂. In a case where a data other than"0" is stored in either of the D₆, D₅, D₄ and D₃ stages in the timershift register 50 an AND gate A₅₉ generates an output "1" during thedigit pulse D₃ to D₆ period, thereby setting the flip-flop circuit F₁₆to produce "1" level output. The output "1" of the flip-flop circuit F₁₆continues up to D₁ ·T₁ time. An AND gate A₆₀ generates an output "1" atthe timing of D₁ ·T₁, setting a flip-flop circuit F₁₇ to produce anoutput "1" from the timing of D₁ ·T₂. Since the flip-flop circuit F₁₆,when set, generates an output "1" at least during the D₁ ·T₁ time an ANDgate 61 generates no output "1". In consequence, the flip-flop circuitF₁₇ maintains the output "1" without being reset as long as the dataother than "0" is present in at least on of the D₆, D₅, D₄ and D₃ stagesin the timer shift register.

When only data "0" is stored in the D₆, D₅, D₄ and D₃ stages in thetimer shift register the flip-flop circuit F₁₆ is not set. Since theflip-flop circuit F₁₇ is only reset by an output "1" as generated at thetiming of D₁ ·T₁ from the AND gate A₆₁, the output of the flip-flopcircuit F₁₇ is at a "0" level.

The data detection of the power level shift register 60 will beexplained below. The reset input of a flip-flop circuit F₁₈ is adaptedto receive a D₃ pulse and in consequence the output of the flip-flopcircuit F₁₈ becomes zero from the D₄ ·T₂ time. When a data other than"0" is present in the power level shift register 60 an AND gate A₆₂generates an output "1" during the digit pulse D₃ period, setting aflip-flop circuit F₁₈ to permit an output "1" to be generated. Theflip-flop circuit F₁₈ produces, when set, "1" level output at leastduring the D₄ ·T₁ period. Accordingly, an AND gate A₆₃ produces "1"level output as to set a flip-flop circuit F₁₉ to produce "1" leveloutput. The output "1" of the flip-flop circuit F₁₉ continues until theflip-flop circuit is reset by an AND gate A₆₄. Since, however, theoutput of the flip-flop circuit F.sub. 18 is at a "1" level during theD₄ ·T₁ period and AND gate A₆₄ generates no output "1". When a dataother than "0" is stored in the power level shift register the flip-flopcircuit F₁₉ is never reset and thus the flip-flop circuit F₁₉ maintainsthe output "1".

When the data of the power level shift register 60 is zero the flip-flopcircuit F₁₈ is not set and the AND gate A₆₄ generates an output "1" attime of D₄ ·T₁, resetting the flip-flop circuit F₁₉ to permit an output"0" to be generated.

The output of the flip-flop circuits F₁₇ and F₁₉ are coupled to an ANDgate A₆₅. Accordingly, the AND gate A₆₅ produces a "1" level output whenthe content stored in each of the power shift register 60 and timershift register 50 is other than zero and produces "0" level output whenthe content of at least one of these shift registers is zero.

When the content of the timer shift register becomes zero as a result ofthe down count operation the output of the data detector 210 becomeszero, resetting the flip-flop circuit F₇ in FIG. 5 to permit a dataentry into the timer shift register 50 and power level shift register60. The AND gate A₃₄ in FIG. 7 is disabled by the output "0" of the datadetector 210 to prevent a supply of subtraction pulses to thesubtractor. The output of the data detector is coupled to the magnetroncontrol circuit 220.

FIG. 17 shows the magnetron control circuit 220. A flip-flop circuit F₂₁is adapted to receive the output of the error entry detector in FIG. 14at its set input and the digit pulse D₂ at its reset input. In a casewhere an error data is present in the timer shift register 50 the outputof the error entry detector becomes "1" during at least one of the digitpulse D₁, D₅ and D₆ periods to set the flip-flop circuit F₂₁. When theflip-flop circuit F₂₁ is set the output thereof becomes "1" during atleast the digit pulse D₂ period and an AND gate A₆₆ generates an output"1" to set a flip-flop circuit F₂₂ to render the Q output thereof "0"level. An AND gate A₆₈ to which the cook key depression signal (CK) andan output of the data detector are coupled is disabled by the output "0"of the flip-flop circuit F₂₂ to cause a timer switch 221 coupled to themagnetron 230 to be rendered OFF. In a case where no error data ispresent in the timer shift register the output of the error entrydetector is at a "0" level and the flip-flop circuit F₂₁ is not set. Inconsequence the Q output of the flip-flop circuit F₂₁ is at a "0" leveland an AND gate A₆₇ generates an output "1" during the digit pulse D₂period, resetting the flip-flop circuit F₂₂ to permit the Q outputthereof to become "1". At this time, if the cook key depression signal(CK) and the data detector output coupled to the AND gate A₆₈ are bothat a "1" level, the timer switch 221 is turned ON to cause the magnetron230 to be operated.

It will be evident from the circuit arrangement of FIG. 17 that when atime data within the maximum time is correctly entered into the timershift register 50 and when a power level setting data other than "0" isset to the power level shift register 60, the timer switch 221 is turnedON by depression of the cook key CK to cause the magnetron 230 to beoperated. When the content in the timer shift register becomes zero as aresult of the down count operation the AND gate A₆₈ is disabled to causethe timer switch 221 to be rendered OFF. An output signal N₁ of the ANDgate A₆₆ is connected to the set input of the flip-flop F₁₀ in FIG. 7 toprevent of supply of a borrow signal from the shift register S₁ to thesubtractor when an erroneous data is present in the timer shift register50.

FIG. 18 shows the buzzer circuit 190 for sounding the buzzer 200 fiveseconds before completion of the down count operation so as to informthe user that the end of the cooking time is drawing near. Although thebuzzer is used in this embodiment, a lamp, bell etc. can be usedinstead.

Upon depression of the cook key CK the flip-flop circuit F₂₃ is reset bythe signal CK(D₂) to generate an output "0". As a result, an AND gateA₆₉ is disabled and the buzzer is not sounded. When the units seconddata is 6 or more an AND gate A₇₀ to which the output of the AND gateA₅₂ in FIG. 14 is coupled produces an output "1" during the digit pulseD₃ period. As a result, a shift register S₅ produces an output "1"during the digit pulse D₄ period and a shift register S₆ generates anoutput "1" during the digit pulse D₅ period. Immediately beforecompletion of the down count operation the tens minute, units minute andtens second data are all zero. In consequence the AND gate A₄₈ in thezero suppression circuit 160 in FIG. 13 generates an output "1" duringthe digit pulse D₅ period. The output of the AND gate A₄₈ is connectedto an AND gate A₇₁. When, as mentioned above, units second data is 6 ormore the output of the shift register S₆ is at a -1" level and theoutput of an inverter I₇ is zero. As a result, the AND gate A₇₁ isdisabled and thus the flip-flop circuit F₂₃ is not set to sound thebuzzer 200. When the units second data becomes 5 the output of the ANDgate A₄₈ in the zero suppression circuit becomes zero and the output ofthe shift register S₆ becomes zero. As a result, the output of theinverter I₇ becomes "1" to enable the AND gate A₇₁. The output of theAND gate A₇₁ becomes "1" during the digit pulse D₅ period, setting theflip-flop circuit F₂₃ to permit the AND gate A₆₉ to be enabled. Inconsequence, the buzzer 200 is started to sound at five seconds beforecompletion of the down count operation. When the down count operation iscompleted the data in the timer shift register 50 becomes zero and theoutput of the data detector becomes zero, disabling the AND gate A₆₉. Asa result, the sounding of the buzzer 200 is stopped at the end of thedown count operation.

FIG. 19 shows the memory cycle pulse generator 70. By depressing a keyon the keyboard 10 a key depression signal KEY (D₂) is fed at the timingof D₂ from the control signal generator 30 to the set input of aflip-flop circuit F₂₄ to the reset input of which is applied the digitpulse D₆. Accordingly, the Q output of the flip-flop circuit F₂₄ becomes"1" during the digit pulse D₃, D₄, D₅ and D₆ periods and becomes zeroduring the digit pulse D₁ and D₂ periods. As a result, a flip-flopcircuit F₂₅ is set by the output of an AND gate A₇₃ which becomes "1"during the digit pulse D₆ period and the Q output of the flip-flopcircuit F₂₅ becomes "1" from the digit pulse D₁ time. A flip-flopcircuit F₂₆ is set by the output of an AND gate A₇₄ one memory cycletime after the flip-flop circuit F₂₅ is set and the output of theflip-flop circuit F₂₆ becomes "1" with one memory cycle time delay fromgeneration of "1" output by the flip-flop circuit F₂₅. In this way, theQ outputs of the flip-flop circuits F₂₅, F₂₆, F₂₇, F₂₈ and F₂₉sequentially become "1" with one memory cycle time delay.

After the key depression the flip-flop circuits F₂₅ to F₂₉ are not resetexcept for the flip-flop circuit F₂₄. When after a key release theflip-flop circuit F₂₄ is reset by the digit pulse D₆ the Q outputthereof becomes zero from the digit pulse D₁ time and the output "0"state is continued. The flip-flop circuit F₂₅ is reset by the output "1"of an AND gate A₇₅ which appears after one memory cycle from the resettime of the flip-flop circuit F₂₄, and the Q output thereof becomes zerofrom the digit pulse D₁ time.

After the key release the flip-flop circuits F₂₅, F₂₆, F₂₇, F₂₈ and F₂₉sequentially become zero with one memory cycle time delay as shown inFIG. 20. It will be apparent that after the key depression an AND gateA₇₆ generates a memory cycle pulse MCA and after the key release an ANDgate A₇₇ generates a memory cycle pulse MCB. An AND gate A₇₈ produces asignal MCA·D₂ upon receipt of the pulses MCA and D₂.

FIG. 21 shows the subtraction pulse generator 90. When the Q output of aflip-flop circuit F₃₀ is at a "1" level an AND gate A₈₀ is enabledduring the positive half cycle of an AC voltage, producing at the outputthereof an output D₁ ·T₁ to set the flip-flop F₃₀. As a result, the Qoutput of the flip-flop circuit F₃₀ becomes zero and the AND gate A₈₀ isdisabled. That is, the D₁ ·T₁ pulse appearing at the output of the ANDgate A₈₀ is one which is first generated during the positive half cycleof the AC supply voltage. The output D₁ ·T₁ of the AND gate A₈₀ issupplied to a shift register S₇ adapted to receive a pulse φ₁ as aread-in pulse and a pulse φ₂ as a readout pulse, and in consequence theoutput of the shift register S₇ is D₁ ·T₂. It will be apparent that inthe case of a 50 Hz AC power supply fifty D₁ ·T₂ pulses per second areobtained and for a 60 Hz AC power supply 60 D₁ ·T₂ pulses are obtained.

FIG. 22 shows the variable power control 240. The outputs of power levelshift register 60 are coupled to a binary-coded-decimal to decimaldecoder 241. The nine outputs of the decoder 241 are respectivelycoupled to switches M₁ to M₉ such as MOS transistors connected in seriesON-OFF rate setting resistors R₁ to R₉ in the time constant circuit of amultivibrator 242. An output of the multivibrator 242 is coupled to atriac 243 which is connected in series timer switches 221a and 221b onthe primary side of a transformer 244 connected across the AC powersupply source. The magnetron 230 is connected across the secondarywinding of the transformer 244.

What we claim is:
 1. A digital control device for controlling cookingtime and power of an electric cooking device comprising:keyboard meanshaving numeral keys, timer key, power level key and cook key; entrymeans coupled to said keyboard means to generate in response to thedepression of one of said numeral keys an output as a numerical datacorresponding to the numerical value of the depressed key; first shiftregister means coupled to the output of said entry means having aplurality of digit stages and adapted to store in response to thedepression of said timer key and numerical keys a time data on a cookingtime of said cooking device which corresponds to the numerical values ofthe depressed numeral keys; second shift register means coupled to theoutput of said entry means to store in response to the depression ofsaid power level key and numeral key a data on a power level of saidcooking device which corresponds to the latter depressed numeral key;digital display means coupled to said first and second shift registermeans to display the data stored in said first and second shift registermeans; subtraction pulse generating means for generating a subtractionpulse for passage of each predetermined unit of time; subtraction meanscoupled to said first shift register means and said subtraction pulsegenerating means and adapted to subtract, for each generated subtractionpulse, a predetermined number from the time data in said first shiftregister means in response to the depression of said cook key; cookingdevice control means coupled to said first shift register means andadapted to operate said cooking device in response to the depression ofsaid cook key after the storage in said first and second shift registersof data on the cooking time and power level and stop the operation ofsaid cooking device when the data in said first shift register become apredetermined number through subtraction; variable power control meanscoupled to said second shift register means and adapted to set saidcooking device to a power corresponding to the data stored in said shiftregister means; error entry detecting means for detecting whether thevalue of a time data entered by said entry means in said first shiftregister means is erroneous; and means responsive to said error entrydetecting means for (1) causing said display means to selectively flashonly an erroneous digit or digits in said time data when said time datain said first register means contains a digit or digits with erroneousvalues, and for (2) maintaining the constant display of any digit with anon-erroneous value.
 2. A control device according to claim 1, furtherincluding means for clearing said first shift register means andpresetting a predetermined number to said second shift register meansupon switching a power supply source ON.
 3. A control device accordingto claim 1, further comprising means for causing said display means toselectively blank only the erroneous digit or digits in said time data.4. A control device according to claim 1 further comprising meansresponsive to said error entry detecting means for stopping asubtraction operation by said subraction means when said time data insaid first shift register means is erroneous.
 5. A control deviceaccording to claim 1 further including means responsive to said errorentry detecting means for causing said cooking device control means toprevent the operation of said cooking device irrespective of thedepression of said cook key.
 6. A control device according to claim 1,in which said first shift register means has first and second digitstages for storing a minute data from said entry means, third and fourthdigit stages for storing a second data from said entry means, and fifthand sixth digit stages to which predetermined numerical data are preset,and there is further provided means for presetting a predeterminednumber to the respective digit stages when the data of the respectivedigit stages becomes a predetermined number during the subtraction ofthe time data in the first shift register means.
 7. A control deviceaccording to claim 1, further including means for entering a data fromsaid entry means in said first shift register in response to thedepression of said timer key and to enter a data from said entry meansin said second shift register means in response to the depression ofsaid power level key.
 8. A control device according to claim 1, furtherincluding means for detecting a non-significant zero or zeros in thetime data in said first shift register means and causing said displayingmeans to blank the non-significant zero or zeros.
 9. A control deviceaccording to claim 1, further including means for clearing said firstshift register means in response to the depression of said timer key.10. A control device according to claim 1, further including means forinforming a user of an approach to the end of the cooking time when thetime data in said first shift register means nears zero during thesubtraction by said subtraction means of the time data in said firstshift register means.
 11. A control device according to claim 1, inwhich said subtraction pulse generating means is adapted to generate inresponse to a 50 or 60 Hz AC supply voltage one subtraction pulse per Hzof the AC voltage, said first shift register means includes first andsecond digit stages for storing a minute data from said entry means,third and fourth digit stages for storing a second data from said entrymeans and fifth and sixth digit stages to which predetermined numbersare preset, respectively, said subtraction means is adapted to effectthe subtraction of the time data in said first shift register meanscomparing the content in a predetermined bit position of said sixthdigit stage with said subtraction pulse and there is further providedmeans for presetting a different number to said sixth stage inaccordance with the frequency of the AC voltage when the content of saidsixth stage becomes a predetermined number during subtraction operation.12. A control device according to claim 1 further comprising means forcausing said subtraction means to stop the subtraction of the time datain said first shift register means when the door of said cooking deviceis opened.
 13. A control device according to claim 1 further comprisingmeans for preventing data entry into said first and second shiftregister means during the subtraction of the time data in said firstshift register means after the depression of said cook key.
 14. Anelectric cooking apparatus comprising:memory means; means accessible bya user for setting time data having a plurality of digits into saidmemory means; digital display means coupled to said memory means fordisplaying the time data in said memory means; an electric cookingdevice; means for operating said electric cooking device during the timeinterval corresponding to the time data set in said memory means; meanscoupled to said memory means for detecting any digit of the time dataset in said memory means having an erroneous value; and means responsiveto said erroneous digit detecting means for causing said digital displaymeans (1) to selectively blank any digit having a said detectederroneous value, and (2) to maintain the constant display of any digithaving a non-erroneous value.
 15. An electric cooking apparatusaccording to claim 14 further comprising means for disabling said meansfor operating said electric cooking device responsive to the detectionof a said erroneous digit of time data entered into said memory means.16. An electric cooking apparatus according to claim 14 furthercomprising means for causing said digital display means to selectivelyflash only the erroneous digit or digits.
 17. An electric cookingapparatus comprising:memory means; means accessible by a user forsetting time data having a plurality of digits into said memory means;digital display means coupled to said memory means for displaying thetime data in said memory means; an electric cooking device; means foroperating said electric cooking device during a time intervalcorresponding to the time data set in said memory means; means coupledto said memory means for detecting any digit of the time data set insaid memory means having an erroneous value; and means responsive tosaid erroneous digit detecting means for causing said digital displaymeans to selectively flash any digit with a said detected erroneousvalue while maintaining the constant display of any digit having anon-erroneous value.
 18. An electric cooking apparatus according toclaim 17 further comprising means for disabling said means for operatingsaid electric cooking device from operating said cooking deviceresponsive to the detection of a said erroneous digit of time dataentered into said memory means.
 19. An electric cooking apparatuscomprising:memory means; means accessible by a user for setting timedata having a plurality of digits into said memory means, the maximumtime settable into said memory means being predetermined; digitaldisplay means coupled to said memory means for displaying the time datain said memory means; an electric cooking device; means for operatingsaid electric cooking device during a time interval corresponding to thetime data set in said memory means; means coupled to said memory meansfor detecting whether the time data set in said memory means by the userexceeds the maximum settable time; and means responsive to saiddetecting means for causing said digital display means to selectivelyflash only an erroneous digit or digits set in said memory means whenthe time data set in said memory means exceeds the maximum settable timeand to maintain the constant display of any non-erroneous digit.
 20. Anelectric cooking apparatus according to claim 19 further comprisingmeans for disabling said means for operating said electric cookingdevice from operating said cooking device responsive to the detection ofa said erroneous digit of time data entered into said memory means. 21.An electric cooking apparatus comprising:a dynamic circulating shiftregister means; keyboard means having numeral keys and a timer key;means responsive to depression of said numeral keys after depression ofsaid timer key for setting time data into said shift register means;digital display means coupled to said shift register means fordisplaying the time data in said shift register means; an electriccooking device; means for operating said electric cooking device duringa time interval corresponding to the time data set in said registermeans; means responsive to depression of said timer key for clearingsaid shift register means; means coupled to said memory means fordetecting any digit of time data set into said shift register means; andmeans responsive to said erroneous digit detecting means for causingsaid digital display means to visually indicate any digit with a saiddetected erroneous value while maintaining the constant display of anynon-erroneous digit.